A key process for forming metal regions within integrated circuits is chemical mechanical polishing (CMP), which involves mechanical polishing of a substrate's active layer surface utilizing an abrasive slurry containing chemicals which react with—and aid in the removal of—the target material on the substrate surface. For tungsten (W) metal layers, for instance, the abrasive slurry employed in chemical mechanical polishing will typically include one or more chemical substances which oxidize the tungsten metal and remove the oxidized tungsten.
A primary benefit of chemical mechanical polishing, in general, is planarization of the upper surface of the integrated circuit structures on the substrate. For conformal layers, in particular, chemical mechanical polishing is useful in producing planar upper surfaces since higher regions of the layer (e.g., those overlying the interlevel dielectric) are removed before lower regions (e.g., those within contact or via openings and the like), and since other materials such as the interlevel dielectric are also removed. Planar upper surfaces facilitate photo-lithography and other processes required for formation of additional layers and/or structures over the polished layer.
Chemical mechanical polishing of tungsten, however, is highly chemical in nature. Tungsten removal by known chemical mechanical polishing processes is quite uniform across the surface of the layer, and is nearly independent of topography. This results in excessive removal of tungsten and “dishing” of the remaining tungsten regions. For example, FIG. 3A illustrates a tungsten metal layer 300 formed conformally over an interlevel dielectric 301, where the dielectric layer 301 is patterned to produce three different types of conductive structures after chemical mechanical polishing: tungsten contacts or vias within openings 302; tungsten interconnects formed by the damascene method within grooves 303 (shown in cross-section and having an extended length not visible in the view illustrated); and tungsten capacitive electrodes for metal oxide semiconductor (MOS) capacitors within trough 304 (also shown in cross-section and having an extended length, which is not visible, for a total area proportional to the desired capacitance).
FIG. 3B illustrates the integrated circuit structure of FIG. 3A at an intermediate point during a chemical mechanical polishing process employed to pattern the tungsten metal layer by removal of the portions overlying interlevel dielectric 301. After partial removal of the tungsten layer by chemical mechanical polishing, tungsten layer 305 remains but, because removal of the tungsten layer by chemical mechanical polishing is largely uniform, is already beginning to dish in lower regions 306 and 307 and is not planarized. Dishing may be particularly pronounced in lower regions 307 having a large area, such as the region 304 for forming MOS capacitor electrode, and less extreme in lower regions having a smaller area (e.g., regions 302 for contacts or vias).
FIG. 3C illustrates the integrated circuit structure of FIG. 3A after completion of a chemical mechanical polishing process employed to pattern the tungsten metal layer, after complete removal of the portions overlying interlevel dielectric 301. The remaining tungsten regions 308 exhibit substantial dishing, and the tungsten layer may be completely removed in some regions 309.
Dishing of tungsten metal layers patterned by chemical mechanical polishing may cause several problems. Dishing of tungsten plugs within contact or via openings exposes the tungsten plug to slurry contamination, which leads to severe interconnect failures. Dishing of interconnects may causes shorts or thin, high resistance points within the conductive path. Dishing of capacitor electrodes, particularly if the tungsten is completely removed at points, may result in a different capacitance than intended.
There is, therefore, a need in the art for a process of mitigating dishing during chemical mechanical polishing of conformal tungsten layers.